1. Field of the Invention
This invention relates to a memory device, and more particularly to a memory device with a packet command for accurately transferring data.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional memory device with a packet command, for example a RAMBUS DRAM. Referring to FIG. 1, the memory device with a packet command includes: a data shift block 20 for receiving data with a packet type from a core block 10 to convert then into serial data in accordance with a clock signal, or receiving serial data from a data pad block and converting the serial data into parallel data to transfer them with a packet type to the core block 10 to be written therein; and an interface block 30 for receiving the data from the data shift block 20 and transferring packed data with 8-bits to the data pad block 40 in series at both negative and positive edges of the clock signals or transferring the data received from the respective data pads to the interface block in series at negative and positive edges of the clock signals.
The above memory device transfers the data of 1 bit to the interface block 30 at the negative edge and the positive edge of each clock signals in the data write, respectively and packets the data with 8 bits during four cycles every data pads. The data packeted with 8 bits for 4 clock cycles every the data pads are transferred to the data shift block 20 and the serial data are converted into the parallel data and then written into the core block 10.
On the other hand, in the data read, the parallel data read from the core block 10 is converted into the serial data trough the data shift block 20 and the serial data from the shift block 20 is transferred into the data pad block 40 through the interface block 30. The data pad block 40 provides the packet data of 8 bits for 4 cycles every data pads in serial. At this time, the data pad block 40 has 16 data pads and it transfers 16 data per 1.25 ns outwardly. Therefore it has 1.6 gigabits per second(GBps).
According to the prior memory device having the above construction, the data pad block 40 basically has 16 data pads, the data of 16.times.18 bits (128 bits) are transferred to the data shift block 20 through the interface block 30. So as to load data from the core block 10 to the data shift block 20, the prior memory device always generates a load signal load_rd_pipe, after a constant time is lapsed following the application of the column packet. Although the data is lately read from the core block 10 due to the process error and so on and the skew is occurred in the data path of 128 bits, the load signal load_rd_pipe is generated from the data shift block 20 at a constant time. Therefore, the data is not accurately transferred to the data shift block 20.